Digitally Self-Calibrated Pipelined Analog-to-Digital Converter

This paper presents a digital capacitor error-averaging calibration technique for pipelined analog-to-digital converters (ADCs). The scheme utilizes a 1.5b/stage digital calibration algorithm and extends it to assess capacitor ratio-mismatches. This is accomplished by using an algorithm similar to analogue capacitor error-averaging (Song, 1988) which is performed in the digital domain. This calibration scheme is demonstrated for a 12-bit pipelined ADC, with 1.5b/stage architecture and 14 identical stages. Gain errors induced by capacitor mismatches (a equiv 3%) are successfully corrected by the proposed algorithm