DocumentCode
1881821
Title
New 1.7kV IGBT chip with fine pattern and optimized buffer layer
Author
Donlon, John F. ; Motto, Eric R. ; Satoh, K. ; Suzuki, K. ; Yoshihiura, Y. ; Takahashi, T.
Author_Institution
Powerex, Inc., Youngwood, PA, USA
fYear
2010
fDate
21-25 Feb. 2010
Firstpage
392
Lastpage
397
Abstract
Since the introduction of the IGBT, improvements in power loss and efficiency have been achieved by applying new technologies. In this paper, refinements in fine pattern processing technology and optimization of the low impurity profile of the buffer layer using thin wafer technology are proposed to further reduce the power loss and improve efficiency in 1.7kV IGBT chips.
Keywords
buffer layers; insulated gate bipolar transistors; low-power electronics; IGBT chip; fine pattern processing technology; low impurity profile optimization; optimized buffer layer; power efficiency; power loss; thin wafer technology; voltage 1.7 kV; Buffer layers; Capacitance; Circuits; Doping profiles; Energy conservation; Impurities; Insulated gate bipolar transistors; Inverters; Motor drives; Ultra large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Applied Power Electronics Conference and Exposition (APEC), 2010 Twenty-Fifth Annual IEEE
Conference_Location
Palm Springs, CA
ISSN
1048-2334
Print_ISBN
978-1-4244-4782-4
Electronic_ISBN
1048-2334
Type
conf
DOI
10.1109/APEC.2010.5433642
Filename
5433642
Link To Document