DocumentCode
188209
Title
A Power-Efficient FPGA-Based Mixture-of-Gaussian (MoG) Background Subtraction for Full-HD Resolution
Author
Tabkhi, Hamed ; Sabbagh, Majid ; Schirner, Gunar
Author_Institution
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
fYear
2014
fDate
11-13 May 2014
Firstpage
241
Lastpage
241
Abstract
This short paper briefly describes an FPGA-based realization of MoG background subtraction operating at fullHD frame resolution. Our HW hand-crafted MoG consists of 77 pipeline stages operating at 148.5 MHz implemented on a Zynq-7000 SoC. The results very high efficiency with a power consumption of less than 500 mW which is 600X more efficient than an embedded software solution.
Keywords
field programmable gate arrays; power consumption; system-on-chip; HW hand-crafted MoG; MoG background subtraction; Zynq-7000 SoC; embedded software solution; field programmable gate array; frequency 148.5 MHz; full-HD frame resolution; mixture-of-Gaussian; pipeline stage; power consumption; power-efficient FPGA; system-on-chip; Computers; Educational institutions; Electronic mail; Pipelines; Power demand; Real-time systems; System-on-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Field-Programmable Custom Computing Machines (FCCM), 2014 IEEE 22nd Annual International Symposium on
Conference_Location
Boston, MA
Print_ISBN
978-1-4799-5110-9
Type
conf
DOI
10.1109/FCCM.2014.76
Filename
6861638
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