DocumentCode :
1882126
Title :
COST reduction algorithm for 8 × 8 lattice reduction aided K-best MIMO detector
Author :
Liao, Chun-Fu ; Huang, Yuan-Hao
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing-Hua Univ., Hsinchu, Taiwan
fYear :
2012
fDate :
12-15 Aug. 2012
Firstpage :
186
Lastpage :
190
Abstract :
This paper proposes a cost reduction algorithm for 8 × 8 lattice-reduction aided K-best multiple-input multiple-output (MIMO) detector. As the MIMO dimension increases, the cost growth and the performance degradation from ML performance become important issues for MIMO detector. This research presents boundary violation decision (BVD), simplified complex enumeration, and differential number (DN) representation to lower the complexity of complex valued lattice reduction aided K-Best detector. The analysis results show that the proposed techniques saves 58% bit registers and 53% combinational circuits with negligible performance degradation compared to ML performance.
Keywords :
MIMO communication; combinational circuits; maximum likelihood detection; K-best MIMO detector; MIMO dimension; bit registers; boundary violation decision; combinational circuits; cost reduction; differential number representation; lattice reduction; maximum likelihood performance; multiple-input multiple-output detector; simplified complex enumeration; Detectors; Hardware; Lattices; MIMO; Quadrature amplitude modulation; Registers; Vectors; K-Best; MIMO detection; lattice reduction;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing, Communication and Computing (ICSPCC), 2012 IEEE International Conference on
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4673-2192-1
Type :
conf
DOI :
10.1109/ICSPCC.2012.6335634
Filename :
6335634
Link To Document :
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