FFT arrays with built-in error correction

Fast Fourier transform (FFT) arrays with built-in error correction are proposed. A time shared TMR scheme is used to achieve the error correcting capability. A quarter of the original FFT array is triplicated and voted in each stage. Therefore the hardware complexity of the error correcting FFT array is a little more than 75% of the original FFT array. This is significant since the error correcting design is smaller than the original. The price for this hardware reduction is that the delay time increases by a factor of 4. However, the throughput penalty can be minimized by pipelining. A technology-independent gate-level analysis of hardware complexity and delay time is included