DocumentCode :
1882231
Title :
CoScale: Coordinating CPU and Memory System DVFS in Server Systems
Author :
Qingyuan Deng ; Meisner, D. ; Bhattacharjee, Arup ; Wenisch, Thomas F. ; Bianchini, R.
fYear :
2012
fDate :
1-5 Dec. 2012
Firstpage :
143
Lastpage :
154
Abstract :
Recent work has introduced memory system dynamic voltage and frequency scaling (DVFS), and has suggested that balanced scaling of both CPU and the memory system is the most promising approach for conserving energy in server systems. In this paper, we first demonstrate that CPU and memory system DVFS often conflict when performed independently by separate controllers. In response, we propose Co Scale, the first method for effectively coordinating these mechanisms under performance constraints. Co Scale relies on execution profiling of each core via (existing and new) performance counters, and models of core and memory performance and power consumption. Co Scale explores the set of possible frequency settings in such a way that it efficiently minimizes the full-system energy consumption within the performance bound. Our results demonstrate that, by effectively coordinating CPU and memory power management, Co Scale conserves a significant amount of system energy compared to existing approaches, while consistently remaining within the prescribed performance bounds. The results also show that Co Scale conserves almost as much system energy as an offline, idealized approach.
Keywords :
queueing theory; storage management chips; CPU; CoScale; DVFS; dynamic voltage; frequency scaling; memory system; server systems; coordination; dynamic voltage and frequency scaling; energy conservation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microarchitecture (MICRO), 2012 45th Annual IEEE/ACM International Symposium on
Conference_Location :
Vancouver, BC
ISSN :
1072-4451
Print_ISBN :
978-1-4673-4819-5
Type :
conf
DOI :
10.1109/MICRO.2012.22
Filename :
6493615
Link To Document :
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