Trade-off between FPGA resource utilization and roundoff error in optimized CSD FIR digital filters

Author

La Serna, Antonio E de ; Soderstrand, Michael A.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA

Volume

1

fYear

1994

fDate

31 Oct-2 Nov 1994

Firstpage

187

Abstract

In this paper, we investigate the trade off between filter order and bits of coefficient precision in fixed-coefficient FIR digital filters utilizing canonical signed digit (CSD) coefficient representation. We demonstrate that the use of optimized CSD coefficients is often the only method for which many practical FIR filters can be prototyped on a single FPGA in today´s technology. Due to finite FPGA resources, our resulting analysis of filter-length, word-length, and CSD bit optimization provides an indication of whether a desired filter performance can be obtained with a specific FPGA logic capacity. We develop a MATLAB algorithm for determining the optimum trade-off between FIR filter length and bits of precision of the coefficients in FIR digital filters

Keywords

FIR filters; application specific integrated circuits; field programmable gate arrays; logic design; roundoff errors; ASIC; CSD bit optimization; FIR filter length; FPGA logic capacity; FPGA resource utilization; Kodek-Steiglitz theorem; MATLAB algorithm; canonical signed digit coefficient representation; filter order; filter performance; minimum bit coefficients; optimized CSD FIR digital filters; roundoff error; word-length; Digital filters; Field programmable gate arrays; Finite impulse response filter; Logic; MATLAB; Optimization methods; Performance analysis; Prototypes; Resource management; Roundoff errors;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 1994. 1994 Conference Record of the Twenty-Eighth Asilomar Conference on

Conference_Location

Pacific Grove, CA

ISSN

1058-6393

Print_ISBN

0-8186-6405-3

Type

conf

DOI

10.1109/ACSSC.1994.471442

Filename

471442