Modeling of digitally controlled voltage regulator modules

This paper proposed small signal models of digital VRMs. At first, the ADC´s conversion delay and digital compensator´s calculation delay are neglected. The focus is placed on the small signal model of the current sampling and the DPWM unit. It is shown that even with a ¿fast¿ controller, the current sampling and DPWM will still introduce some delay to the loop. Then the conversion and calculation delays are considered. Two time periods, T_1ff and T_1rr, are employed to describe the delay effects in the control loop. It is observed that the total delay in the loop is an integral number of sampling periods, which is never reported by any other literatures. The proposed model consolidates these to one delay term and the value can be found through a pre-determined lookup table. Design guidelines of digital VRMs are provided. Simulation and experimental results verify the validity of this model.