• DocumentCode
    1882688
  • Title

    MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP

  • Author

    Khubaib, K. ; Suleman, M.A. ; Hashemi, M. ; Wilkerson, Chris ; Patt, Y.N.

  • Author_Institution
    Univ. of Texas at Austin, Austin, TX, USA
  • fYear
    2012
  • fDate
    1-5 Dec. 2012
  • Firstpage
    305
  • Lastpage
    316
  • Abstract
    Several researchers have recognized in recent years that today\´s workloads require a micro architecture that can handle single-threaded code at high performance, and multi-threaded code at high throughput, while consuming no more energy than is necessary. This paper proposes Morph Core, a unique approach to satisfying these competing requirements, by starting with a traditional high performance out-of-order core and making minimal changes that can transform it into a highly-threaded in-order SMT core when necessary. The result is a micro architecture that outperforms an aggressive 4-way SMT out-of-order core, "medium" out-of-order cores, small in-order cores, and Core Fusion. Compared to a 2-way SMT out-of-order core, Morph Core increases performance by 10% and reduces energy-delay-squared product by 22%.
  • Keywords
    multi-threading; multiprocessing systems; 4-way SMT out-of-order core; CoreFusion; MorphCore; energy-efficient microarchitecture; high performance ILP; high throughput TLP; instruction-level parallelism; medium out-of-order cores; multithreaded code; single-threaded code; small in-order cores; thread level parallelism;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microarchitecture (MICRO), 2012 45th Annual IEEE/ACM International Symposium on
  • Conference_Location
    Vancouver, BC
  • ISSN
    1072-4451
  • Print_ISBN
    978-1-4673-4819-5
  • Type

    conf

  • DOI
    10.1109/MICRO.2012.36
  • Filename
    6493629