High-speed cosine generator

Author

McIntosh, James A. ; Swartzlander, Earl E., Jr.

Author_Institution

Nat. Instrum. Corp., Austin, TX, USA

Volume

1

fYear

1994

fDate

31 Oct-2 Nov 1994

Firstpage

273

Abstract

An 8-bit high-speed cosine generator circuit was designed and simulated. Speed and area estimates were made for 16-, 24-, 32-, 40-, 48-, 56-, and 64-bit designs. The basis of the cosine generator design is stages of a half-angle cosine function preceded by a low order Taylor series approximation of cos (θ/2^N). This turns out to be a decent approximation. The big difference between this and most other methods is that a lookup ROM for the first order approximations is avoided

Keywords

Chebyshev approximation; approximation theory; digital arithmetic; polynomials; series (mathematics); signal processing; 16 bit; 24 bit; 32 bit; 40 bit; 48 bit; 56 bit; 64 bit; 8 bit; Chebyshev polynomial; approximation; area estimates; cosine generator design; first order approximations; half-angle cosine function; high-speed cosine generator; low order Taylor series approximation; signal processing; speed estimates; trigonometric functions; Bridge circuits; Chebyshev approximation; Circuit simulation; Equations; Instruments; Polynomials; Read only memory; Signal processing; Table lookup; Taylor series;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 1994. 1994 Conference Record of the Twenty-Eighth Asilomar Conference on

Conference_Location

Pacific Grove, CA

ISSN

1058-6393

Print_ISBN

0-8186-6405-3

Type

conf

DOI

10.1109/ACSSC.1994.471459

Filename

471459