• DocumentCode
    1883088
  • Title

    Designing a Programmable Wire-Speed Regular-Expression Matching Accelerator

  • Author

    Lunteren, J.V. ; Hagleitner, Christoph ; Heil, Ted ; Biran, G. ; Shvadron, U. ; Atasu, Kubilay

  • Author_Institution
    IBM Res. - Zurich, Zurich, Switzerland
  • fYear
    2012
  • fDate
    1-5 Dec. 2012
  • Firstpage
    461
  • Lastpage
    472
  • Abstract
    A growing number of applications rely on fast pattern matching to scan data in real-time for security and analytics purposes. The RegX accelerator in the IBM Power Edge of NetworkTM (PowerEN) processor supports these applications using a combination of fast programmable state machines and simple processing units to scan data streams against thousands of regular-expression patterns at state-of-the-art Ethernet link speeds. RegX employs a special rule cache and includes several new micro-architectural features that enable various instruction dispatch and execution options for the processing units. The architecture applies RISC philosophy to special-purpose computing: hardware provides fast, simple primitives, typically performed in a single cycle, which are exploited by an intelligent compiler and system software for high performance. This approach provides the flexibility required to achieve good performance across a wide range of workloads. As implemented in the PowerENTM processor, the accelerator achieves a theoretical peak scan rate of 73.6 Gbit/s, and a measured scan rate of about 15 to 40 Gbit/s for typical intrusion detection workloads.
  • Keywords
    cache storage; computer network security; finite state machines; local area networks; pattern matching; program compilers; reduced instruction set computing; Ethernet link speeds; IBM Power Edge of Network processor; PowerEN processor; RISC; RegX accelerator; analytics; cache storage; data stream scanning; grammable state machines; instruction dispatch; instruction execution; intelligent compiler; microarchitectural features; network intrusion detection; pattern matching; peak scan rate; processing units; programmable wire-speed regular-expression matching accelerator design; scan rate measurement; security; system software;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microarchitecture (MICRO), 2012 45th Annual IEEE/ACM International Symposium on
  • Conference_Location
    Vancouver, BC
  • ISSN
    1072-4451
  • Print_ISBN
    978-1-4673-4819-5
  • Type

    conf

  • DOI
    10.1109/MICRO.2012.49
  • Filename
    6493642