Detailed study of a 5 V/1 V, four stage switched capacitor converter suitable for integration

Operation of a 5 V/1 V Switched Capacitor DC/DC converter suitable for integration in a 0.18//spl mu/m CMOS technology is analysed in detail. Equations for non linear voltages across capacitors and output are derived using first principles for steady state operation of the converter. The behaviour of the converter during the switching transition periods, which has previously been neglected, can have a significant impact on performance in high frequency operation is included. The operation of the converter was simulated in PSPICE and results are compared with the analytical solutions to validate the first principles studies. The analytical equations are used to evaluate the sensitivity of different parameters, including parasitics, on the average and the ripple of the output voltage. These equations provide a faster approach to evaluating the operation of the converter without having to resort to a trial and error simulation approach for optimum design.