DocumentCode
1883457
Title
A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache
Author
Barth, Jens ; Plass, Donald ; Nelson, Edward ; Hwang, Chang-Sing ; Fredeman, G. ; Sperling, Michael ; Mathews, A. ; Reohr, W. ; Nair, Kalyani ; Cao, Nianxia
Author_Institution
IBM, Essex Junction, VT, USA
fYear
2010
fDate
7-11 Feb. 2010
Firstpage
342
Lastpage
343
Abstract
This paper presents a 1.7 ns-random-cycle SOI embedded-DRAM macro developed for the POWER7¿ high-performance microprocessor and introduces enhancements to the micro-sense-amplifier (¿SA) architecture. The macro enables a 32 MB on-chip L3 cache, eliminating delay, area and power from the off-chip interface.
Keywords
DRAM chips; amplifiers; cache storage; microprocessor chips; silicon-on-insulator; POWER7TM; SOI; Si; embedded DRAM; high-performance microprocessor; microsense-amplifier; on-chip L3 cache; size 45 nm; storage capacity 32 Mbit; time 1.7 ns; Capacitance; Decoding; Degradation; Delay; Microprocessors; Noise measurement; Random access memory; Timing; Voltage; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
978-1-4244-6033-5
Type
conf
DOI
10.1109/ISSCC.2010.5433814
Filename
5433814
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