A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS

Author

Spagna, F. ; Lidong Chen ; Deshpande, Manohar ; Yongping Fan ; Gambetta, D. ; Gowder, S. ; Iyer, Srikrishna ; Kumar, Ravindra ; Kwok, P. ; Krishnamurthy, Ram ; Chien-Chun Lin ; Mohanavelu, R. ; Nicholson, R. ; Ou, Jinping ; Pasquarella, M. ; Prasad, K. ;

Author_Institution

Intel, Santa Clara, CA, USA

fYear

2010

fDate

7-11 Feb. 2010

Firstpage

366

Lastpage

367

Abstract

An 11.8 Gb/s transceiver with 3-tap FIR TX and adaptively equalized RXis implemented in a 32 nm CMOS process. The RX features a continuous-time LE with AGC, a 4-tap DFE and baud-rate timing recovery. The transceiver achieves a BER<2 Ã— 10^-15 with PRBS23 over a 24" PCB trace with 25 dB loss at 5.9 GHz. The TX/RX lane occupies 0.155 mm² and consumes 78 mW from a 0.95 V supply when operating at 11.8 Gb/s.

Keywords

CMOS integrated circuits; FIR filters; adaptive signal processing; automatic gain control; clock and data recovery circuits; decision feedback equalisers; mixed analogue-digital integrated circuits; synchronisation; transceivers; CMOS; FIR transmitter; adaptive receiver equalization; adaptively equalized receiver; automatic gain control; baud rate timing recovery; bit rate 11.8 Gbit/s; clock and data recovery; decision feedback equalizer; frequency 5.9 GHz; power 78 mW; serial link transceiver; size 32 nm; voltage 0.95 V; Adaptive equalizers; Bit error rate; Circuit testing; Clocks; Decision feedback equalizers; Integrated circuit interconnections; LAN interconnection; Phase estimation; Timing; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4244-6033-5

Type

conf

DOI

10.1109/ISSCC.2010.5433823

Filename

5433823