Computer aided electrical modeling of VLSI packages

A software tool for modeling package parasitics and generating equivalent circuit files is described. This tool is a collection of software modules and generates SPICE-like netlists for single and multilayer packages (plastic/ceramic). The package parasitics are evaluated using geometry and material properties extracted directly from the existing CAD (computer-aided design) package database. Using this tool, the chip designer can model the combined device, package, and system environment. Results for modeled package parasitics are compared to experimental values, and results of simulations for noise generated on the i486 processor package ground plane due to simultaneously switching signal lines driving a system load are presented