Title :
FPGA based prototyping of next generation forward error correction
Author :
Mizuochi, T. ; Konishi, Y. ; Miyata, Y. ; Inoue, T. ; Onohara, K. ; Kametani, S. ; Sugihara, T. ; Kubo, K. ; Kobayashi, T. ; Yoshida, H. ; Ichikawa, T.
Author_Institution :
Mitsubishi Electr. Corp., Japan
Abstract :
The concatenation of LDPC and RS codes has been demonstrated using a real-time FPGA prototype. A net coding gain of 9.0 dB for 31.3-Gb/s was achieved with 20.5% redundancy for an input BER of 10-2.
Keywords :
Reed-Solomon codes; error statistics; field programmable gate arrays; forward error correction; parity check codes; BER; FPGA; LDPC codes; RS codes; Reed-Solomon codes; bit error rate; bit rate 31.3 Gbit/s; forward error correction; gain 9.0 dB; low density parity check codes; net coding gain; Circuit testing; Decoding; Field programmable gate arrays; Forward error correction; High speed optical techniques; Large scale integration; Optical noise; Parity check codes; Prototypes; Redundancy;
Conference_Titel :
Optical Communication, 2009. ECOC '09. 35th European Conference on
Conference_Location :
Vienna
Print_ISBN :
978-1-4244-5096-1
