Title :
A 2×25Gb/s deserializer with 2∶5 DMUX for 100Gb/s ethernet applications
Author :
Ke-Chung Wu ; Jri Lee
Author_Institution :
Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A 2 × 25 Gb/s deserializer for 100 Gb/s Ethernet is implemented in 65 nm CMOS technology. Employing regulated limiting amplifiers, full-rate CDRs, a built-in clock generator, and a 2:5 DMUX, this two-channel prototype achieves BER < 10-12 with 20 mVpp input sensitivity while consuming a total power of 510 mW.
Keywords :
CMOS integrated circuits; amplifiers; clock and data recovery circuits; demultiplexing; error statistics; local area networks; BER; CMOS technology; DMUX; Ethernet; amplifier; bit rate 100 Gbit/s; built-in clock generator; deserializer; full-rate CDR; power 510 mW; size 65 nm; voltage 20 mV; Bandwidth; Bit error rate; CMOS technology; Circuits; Clocks; Ethernet networks; Jitter; Optical receivers; Sampling methods; Voltage;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5433827
