On the Design of a Path-Setup Architecture for Exploiting Hybrid Photonic-Electronic NoCs

Future many-core systems will require energy-efficient, high-throughput and low-latency communication architectures. Silicon Photonics appears today as a promising solution to achieve these goals. However, the photonics inability to perform inflight buffering and logic suggests the use of Hybrid Photonic-Electronic architectures. In order to exploit the full potential of photonics, it is essential to thoroughly design the Path-Setup architecture, which is the primary source of performance degradation and power consumption. In this paper, we propose a new power-aware path-setup protocol able to put allocated circuits on a stand-by state, rapidly recovering them when needed. We compare in terms of performance and energy consumption some path-setup architectural solutions that differ from each other in the routing algorithm, the path-setup protocol and the deadlock avoidance technique. The results show that the proposed protocol outperforms other solutions in terms of performance and energy efficiency. In addition, this comparison will help many-core system designers to select the most appropriate path-setup architecture according to traffic characteristics and network size.