Title :
High radix booth multipliers using reduced area adder trees
Author :
Gallagher, W. Lynn ; Swartzlander, Earl E., Jr.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
fDate :
31 Oct-2 Nov 1994
Abstract :
The reduced area multiplier, the Wallace multiplier, and the Dadda (1965) multiplier each offer fast multiplication of signed binary numbers with the use of a large adder tree and a carry lookahead adder. However, their complexity makes them undesirable for some applications. A Booth (1951) multiplier, on the other hand, offers simplicity and flexibility, by both breaking a multiplication up into pieces, and by allowing the size of the pieces to be chosen. Unfortunately, Booth multipliers become difficult to design for higher radices. The use of a fast adder tree, such as that found in a reduced area multiplier, permits straightforward design of very high radix Booth multipliers. Increasing the radix of a Booth multiplier in this manner results in large increases in speed with reasonable hardware cost
Keywords :
adders; carry logic; digital arithmetic; multiplying circuits; Booth multiplier; Dadda multiplier; Wallace multiplier; carry lookahead adder; fast multiplication; high radix booth multipliers; reduced area adder trees; signed binary numbers; Algorithm design and analysis; Costs; Counting circuits; Hardware; Logic;
Conference_Titel :
Signals, Systems and Computers, 1994. 1994 Conference Record of the Twenty-Eighth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
0-8186-6405-3
DOI :
10.1109/ACSSC.1994.471512