A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS

A fractional-N digital PLL with spread-spectrum capability occupies 190×200 ¿m² in 65 nm CMOS. It features a 190-to-4270 MHz digitally controlled ring oscillator and does not use any TDC. The period jitter is 1.4 ps_rms (15 ps_pp) at 3 GHz and 8.4 ps_rms (75 ps_pp) at 375 MHz. The PLL dissipates 1.85 mW plus 3.3 mW/GHz from 1.3 V and 1.1 V dual supplies.