Title :
Circuit driven delay optimization of EMODL carry lookahead adders
Author :
Wang, J. ; Wang, Z. ; Jullien, G.A. ; Bizzan, S.S. ; Luo, W. ; Miller, W.C.
Author_Institution :
VLSI Res. Group, Windsor Univ., Ont., Canada
fDate :
31 Oct-2 Nov 1994
Abstract :
Delay minimization of carry look-ahead adders using the enhanced multiple output domino logic (EMODL), is investigated. Delay versus tree height, using an analytical transistor sizing technique, is analyzed, and the trade-off between the tree height and the number of stages is discussed. Four architectures for a 32-bit adder are compared at the layout level and experiments show that the number of stages is more critical for delay optimization. Mask level simulations predict an aggressive 2.1 ns critical path for the best architecture using a 1.2 micron CMOS technology. The simulation procedure is verified by fabrication
Keywords :
CMOS logic circuits; adders; carry logic; circuit analysis computing; circuit optimisation; digital arithmetic; integrated circuit layout; 1.2 micron; 1.2 micron CMOS technology; 32 bit; EMODL carry lookahead adders; adder; analytical transistor sizing technique; architectures; circuit driven delay optimization; delay minimization; experiments; fabrication; layout level; mask level simulations; multiple output domino logic; simulation procedure; stages; tree height; Adders; Boolean functions; CMOS technology; Circuit simulation; Computational modeling; Delay; Fabrication; Logic circuits; Logic design; Very large scale integration;
Conference_Titel :
Signals, Systems and Computers, 1994. 1994 Conference Record of the Twenty-Eighth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
0-8186-6405-3
DOI :
10.1109/ACSSC.1994.471513
