DocumentCode
1884285
Title
A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC
Author
Tokairin, T. ; Okada, Masayuki ; Kitsunezuka, M. ; Maeda, T. ; Fukaishi, M.
Author_Institution
NEC, Kawasaki, Japan
fYear
2010
fDate
7-11 Feb. 2010
Firstpage
470
Lastpage
471
Abstract
A 2.1-to-2.8 GHz low-power all-digital PLL with a time-windowed single-shot pulse-controlling 2-step TDC is presented. The test-chip is implemented in 90 nm CMOS and exhibits in-band phase noise of -105 dBc/Hz with 500 kHz loop-bandwidth and out-of-band noise of -115 dBc/Hz at 1 MHz offset. The chip draws 8.1 mA from a 1.2 V supply.
Keywords
CMOS digital integrated circuits; frequency convertors; frequency synthesizers; CMOS; all-digital frequency synthesizer; complementary metal-oxide-semiconductor; current 8.1 mA; frequency 2.1 GHz to 2.8 GHz; in-band phase noise; single shot pulse-controlling TDC; size 90 nm; test chip; time to digital converter; time-windowed TDC; voltage 1.2 V; Detectors; Energy consumption; Flip-flops; Frequency synthesizers; Inverters; Phase noise; Propagation delay; Pulse generation; Quantization; Signal generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
978-1-4244-6033-5
Type
conf
DOI
10.1109/ISSCC.2010.5433843
Filename
5433843
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