• DocumentCode
    1884344
  • Title

    A 3.5GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation

  • Author

    Weltin-Wu, Colin ; Temporiti, Enrico ; Baldi, Daniele ; Cusmai, Matteo ; Svelto, Francesco

  • Author_Institution
    Columbia Univ., New York, NY, USA
  • fYear
    2010
  • fDate
    7-11 Feb. 2010
  • Firstpage
    468
  • Lastpage
    469
  • Abstract
    We present a 3.5 GHz fractional-N ADPLL with a 3.4 MHz bandwidth operating from a 35 MHz reference. Using a dithering algorithm and feedforward compensation around the TDC results in spurious performance better than -58 dBc, and in-band phase noise of -101 dBc/Hz. The IC with fully integrated calibration logic occupies 0.44 mm2 in 65 nm CMOS, and consumes 8.7 mW.
  • Keywords
    CMOS integrated circuits; calibration; compensation; field effect MMIC; microwave circuits; phase locked loops; CMOS integrated circuit; TDC dithering; all digital phase locked loop; bandwidth 3.4 MHz; feedforward compensation; fractional spur suppression; fractional-N ADPLL; frequency 3.5 GHz; fully integrated calibration logic; in-band phase noise; power 8.7 mW; size 65 nm; wideband ADPLL; 1f noise; Calibration; Counting circuits; Delay; Frequency; Noise cancellation; Phase noise; Semiconductor device measurement; Table lookup; Wideband;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    978-1-4244-6033-5
  • Type

    conf

  • DOI
    10.1109/ISSCC.2010.5433846
  • Filename
    5433846
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1884344