Title :
A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor
Author :
Pille, J. ; Wendel, Dieter ; Wagner, O. ; Sautter, R. ; Penth, W. ; Froehnel, T. ; Buettner, S. ; Torreiter, O. ; Eckert, Melanie ; Paredes, J. ; Hrusecky, D. ; Ray, Debtanu ; Canada, M.
Author_Institution :
IBM, Boeblingen, Germany
Abstract :
The POWER7TM microprocessor features a 32 kB L1 data cache with a 2R and banked-1W functionality using a 6T-SRAM cell. Read/write collision is intercepted inside the array with write-over-read priority. The array-specific power supply improves SRAM cell stability and performance while reducing the logic voltage level. The macro is fabricated in a 45nm CMOS SOI technology.
Keywords :
CMOS integrated circuits; cache storage; microprocessor chips; random-access storage; silicon-on-insulator; 6T-SRAM cell; CMOS SOI technology; POWER7 microprocessor; SRAM cell stability; array-specific power supply; data cache; logic voltage level; read/write collision; write-over-read priority; Circuits; Clocks; Energy consumption; Frequency; Hardware; Logic arrays; Logic devices; Random access memory; Stability; Voltage control;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5433849
