DocumentCode
1884792
Title
A Clamping Circuit Architecture Implementing Charges Injection Reduction Techniques
Author
Laquerre, Pierre ; Bernal, Olivier ; Lescure, Marc
Author_Institution
Lab. d´´electronique de l´´ENSEEIHT, Toulouse
fYear
2006
fDate
24-27 April 2006
Firstpage
1473
Lastpage
1477
Abstract
By analyzing the classic clamping circuit, it is shown that the analog switches limit the precision of such a circuit, to 12 bits for 10Msamples/s signals, using a low-voltage CMOS 0.35mum technology. This paper presents an improved clamping architecture that overcomes these limitations. Precisions on the order of 16 bits and more can then be reached, the operational amplifiers being the new limiting factor
Keywords
CCD image sensors; CMOS analogue integrated circuits; low-power electronics; operational amplifiers; 0.35 micron; CCD sensor; CMOS technology; analog switches; charge injection; clamping circuit architecture; differential amplifier; operational amplifiers; CMOS technology; Charge coupled devices; Clamps; Data mining; MOS capacitors; Parasitic capacitance; Signal processing; Switches; Switching circuits; Voltage; CCD sensor; Charge injection; Clamp; Differential amplifier; Low-voltage CMOS;
fLanguage
English
Publisher
ieee
Conference_Titel
Instrumentation and Measurement Technology Conference, 2006. IMTC 2006. Proceedings of the IEEE
Conference_Location
Sorrento
ISSN
1091-5281
Print_ISBN
0-7803-9359-7
Electronic_ISBN
1091-5281
Type
conf
DOI
10.1109/IMTC.2006.328641
Filename
4124589
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