Digital control of single-phase power factor preregulators suitable for smart-power integration

This paper proposes a fully digital control of boost power factor preregulators (PFPs) with input voltage estimation that is suitable for smart-power integration. The proposed solution features a minimum pin count by avoiding direct sensing of the input voltage for the construction of the internal current reference signal and by sensing the output voltage through a direct sampling of the voltage across the power switch during its off interval at the line voltage peak. The control algorithm requires the estimation of the rectified input voltage, that is simply done by exploiting the integral part of the current loop PI regulator, and a PLL (phase-looked-loop) synchronization with the estimated line frequency for sampling the output voltage and rejecting the low-frequency output voltage ripple. The provisions needed to ensure correct output voltage sensing, even during transient and light-load conditions, are also discussed. Experimental results on a single-phase boost PFP show the properties of the proposed approach.