• DocumentCode
    1885160
  • Title

    Implementation of ternary logic gates using FGMOS

  • Author

    Gopal, Perni Venu ; Narkhede, Satish ; Sasikala, G.

  • Author_Institution
    Vel Tech Dr.RR & Dr.SR Tech. Univ. & CDAC Acts, Pune, India
  • fYear
    2015
  • fDate
    6-8 May 2015
  • Firstpage
    275
  • Lastpage
    279
  • Abstract
    Inthis paper we present the ternary logic gates implementation using FGMOS (Floating gate MOSFET) also calledMIFG MOSFET (Multi input floating gate MOSFET). Implementation using ternary logic have advantage than binary logic implementation in terms of more information capability, reduced interconnections and reduction in chip area. MIFG MOSFETs design reduces transistor count as a result area of chip will reduce. Ternary logic gates using MIFG MOSFETs reduces transistor count compared with CMOS design and CNTFET based designs.
  • Keywords
    MOSFET; logic gates; ternary logic; FGMOS; MIFG MOSFET; floating gate MOSFET; multi input floating gate MOSFET; ternary logic gates; CMOS integrated circuits; Integrated circuit interconnections; Inverters; Logic gates; MOSFET; Multivalued logic; Binary logic; CMOS and CNTFET; FGMOS; MIFG MOSFET; Ternary logic;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Smart Technologies and Management for Computing, Communication, Controls, Energy and Materials (ICSTM), 2015 International Conference on
  • Conference_Location
    Chennai
  • Print_ISBN
    978-1-4799-9854-8
  • Type

    conf

  • DOI
    10.1109/ICSTM.2015.7225427
  • Filename
    7225427