The scalability of decoupled multiprocessors

We consider the ability of the technique of decoupling to improve the scalability of multiprocessors which have physically distributed memory but which support a shared memory model of computation. We consider the performance of a variety of similar such architectures; those with and without caching and those with and without decoupling. As a metric of scalability we focus on the speedup of these architectures while executing a suite of parallel scientific applications. We show that decoupling can play a substantial role in improving the scalability of such an architecture. Furthermore the additional technique of caching with hardware coherence can further improve this scalability in the face of high latency memory access