A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction

7 Gb/s/pin operation without bank group restriction in a GDDR5 SDRAM is achieved by skewed control logic and current-mode I/O sense amplifiers with regular calibration from replica impedance monitors. The bank-to-bank active time is shortened to 2.5 ns by a FIFO-based BLSA enabler, 2.0 ns latency V_PP generator and active jitter canceler. The chip is fabricated in a 50 nm DRAM process in a 61.6 mm² die area.