A dedicated data flow architecture for hardware compilation

Author

Naini, Majid Mojtabavi

Author_Institution

Dept. of Electr. & Comput. Eng., Florida Atlantic Univ., Boca Raton, FL, USA

Volume

1

fYear

1989

fDate

3-6 Jan 1989

Firstpage

181

Abstract

A dedicated data-flow architecture that has been designed to be a part of a hardware compiler is described. This machine evaluates attribute grammars in a data-flow fashion by accepting their reverse-dependency graph, which is similar to a data-flow graph. The outputs and the results of these evaluations are sent to the other components for later use. The machine is believed to be the first dedicated data-flow architecture suggested for this purpose. It takes advantage of parallelism at two levels: first, the components of the machine are organized in a pipeline fashion and can run concurrently; second, the execution of the instructions is done in parallel as well

Keywords

circuit layout CAD; parallel architectures; attribute grammars; dedicated data flow architecture; hardware compilation; parallelism; reverse-dependency graph; Computer architecture; Computer languages; Costs; Flow graphs; Hardware; Parallel processing; Pipelines; Production; Real time systems; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

System Sciences, 1989. Vol.I: Architecture Track, Proceedings of the Twenty-Second Annual Hawaii International Conference on

Conference_Location

Kailua-Kona, HI

Print_ISBN

0-8186-1911-2

Type

conf

DOI

10.1109/HICSS.1989.47158

Filename

47158