A SystemC modeling and simulation methodology for fast and accurate parallel MPSoC simulation

Due to the growing complexity of embedded systems, simulation becomes an increasingly time-consuming task. Especially detailed simulation of so called Multi-Processor System-on-Chips (MPSoCs) is afflicted with extremely long runtimes and makes verification and debugging extraordinary expensive. In this work, a SystemC/TLM based methodology for accelerating simulation of NoC-based MPSoCs is presented that combines advantages of both, multi-abstraction level modeling and parallel execution on multi-core hosts. It integrates a parallel discrete event modeling paradigm with the concept of lightweight schedulers. The approach is evaluated on different host platforms by means of a realistic model. Results demonstrate that the approach can provide significant speedups of two orders of magnitude versus sequential RTL simulation, while preserving analyzability and exhibiting a moderate loss accuracy.