Improving the methodology to build non-series-parallel transistor arrangements

This paper presents an improvement in our previous methodology to generate efficient transistor networks. The proposed method applies graph-based optimizations and is capable to deliver series-parallel and non-series-parallel arrangements with reduced transistor count. The main feature of our methodology is the possibility to avoid greedy choices during the beginning of the optimization process. This property is associated to an edges compression technique that also contributes to minimize the bad effect of the greedy choices. Performed experiments have demonstrated the efficiency of this methodology when comparing to other available techniques.