Efficient bus arbitration protocol for SoC design

Improvement in the electronic devices and IC technologies has led to the need of fast arbiter design and encouragement of SoC design. Thus, an arbiter is required that matches with the SoC design speed. This paper presents a configurable arbiter for n users. The proposed design is implemented using Round Robin technique. Result and simulation analysis has been performed for 8, 16 and 18 users. The verification of the design functionality has been performed by RTL simulation. Result analysis indicates the high speed and efficient design of the proposed arbiter as compared to the existing arbiters. The maximum operating frequency obtained is 236MHz.