Stepped segment LFSR for low test power BIST

Author

Bhargav Ram, B.V. ; Harish, G. ; Yelampalli, Shiva

Author_Institution

VLSI Dept., UTL Technol. Ltd., Bangalore, India

fYear

2015

fDate

6-8 May 2015

Firstpage

424

Lastpage

427

Abstract

The power during testing is very greater than the functional power in the BIST which affects the reliability of the chip and it is due to the less correlation between the test patterns generated by TPG. In this paper a new low transition TPG is proposed which allows maximum 2 transitions between the consecutive test patterns by stepped segment activation of LFSR. From the experiments conducted on ISCAS´89 benchmark circuits the proposed LFSR reduces the testing power averagely by 19.63% with little reduction in fault coverage.

Keywords

automatic test pattern generation; built-in self test; integrated circuit reliability; low-power electronics; chip reliability; functional power; low test power BIST; low transition TPG; stepped segment LFSR; test patterns; Built-in self-test; Circuit faults; Clocks; Multiplexing; Test pattern generators; Very large scale integration; Automatic Test Equipment (ATE); Circuit under Test (CUT); Design For Testability (DFT); Linear Feedback Shift Register (LFSR); Output Response Analyzer (ORA); Self-Test Using MISR/Parallel Shift Register Sequence Generator (STUMPS); Test pattern generator (TPG);

fLanguage

English

Publisher

ieee

Conference_Titel

Smart Technologies and Management for Computing, Communication, Controls, Energy and Materials (ICSTM), 2015 International Conference on

Conference_Location

Chennai

Print_ISBN

978-1-4799-9854-8

Type

conf

DOI

10.1109/ICSTM.2015.7225454

Filename

7225454