Title :
An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM
Author :
Miura, Naruhisa ; Kasuga, K. ; Saito, Masato ; Kuroda, Tadahiro
Author_Institution :
Keio Univ., Yokohama, Japan
Abstract :
An 8 Tb/s 1 pJ/b 0.8 mm2/Tb/s inductive-coupling interface between 65 nm CMOS GPU and 0.1 ¿m DRAM is developed. BER <10-16 operation is examined in 1024-bit parallel links. Compared to the latest wired 40 nm DRAM interface, the bandwidth is increased 32×, and the energy consumption and layout area are reduced by 8× and 22×, respectively.
Keywords :
CMOS analogue integrated circuits; DRAM chips; coprocessors; coupled circuits; energy consumption; error statistics; BER; CMOS GPU; DRAM; QDR inductive-coupling interface; bit rate 8 Tbit/s; energy consumption; layout area; parallel links; size 0.1 mum; size 65 nm; word length 1024 bit; Bandwidth; Bit error rate; Circuits; Clocks; Energy consumption; Hysteresis; MOS devices; Random access memory; Transceivers; Voltage;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5433909
