A 90nm 4Mb embedded phase-change memory with 1.2V 12ns read access time and 1MB/s write throughput

Author

De Sandre, G. ; Bettini, Luca ; Pirola, A. ; Marmonier, L. ; Pasotti, M. ; Borghi, M. ; Mattavelli, Paolo ; Zuliani, Paola ; Scotti, L. ; Mastracchio, G. ; Bedeschi, F. ; Gastaldi, R. ; Bez, Riadh

Author_Institution

STMicroelectronics, Agrate Brianza, Italy

fYear

2010

fDate

7-11 Feb. 2010

Firstpage

268

Lastpage

269

Abstract

A 90 nm 4 Mb embedded phase-change memory (PCM) is presented, demonstrating the feasibility of PCM integration with 3 masks overhead in a 6-ML standard CMOS process. Using a low-voltage NMOS transistor as a cell selector leads to a 0.29 ??m² cell size. A 1.2 V low-voltage read operation achieves a 12 ns access time. The 3 mm² macro features a random write throughput of 1 MB/s and a mode to increase write throughput to 4 MB/s.

Keywords

CMOS memory circuits; low-power electronics; memory architecture; phase change memories; cell selector; complementary metal-oxide-semiconductor; embedded phase-change memory; low voltage NMOS transistor; low voltage read operation; read access time; size 90 nm; standard CMOS process; time 12 ns; voltage 1.2 V; word length 4000000 bit; write throughput; Circuits; Decoding; MOS devices; Nonvolatile memory; Phase change materials; Phase change memory; Read-write memory; Switches; Throughput; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4244-6033-5

Type

conf

DOI

10.1109/ISSCC.2010.5433911

Filename

5433911