Design and Implementation of a 1.5Gsps Digital Channelized Receiver

Based on the derivation of the efficient implementation structure of the frequency domain polyphase filter digital channelized receiver, a digital channelized receiver was achieved on the hardware platform with I/Q sampling, 1500Msps, 64channels. In order to ensure good performance of the system, optimization of the processor speed and processor resources was fully considered during the design process of the whole system. The actual ultra-wideband signal test results show that the digital channelized receiver is in good performance.