A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance

Author

Tschanz, James ; Bowman, Keith ; Shih-Lien Lu ; Aseron, Paolo ; Khellah, Muhammad M. ; Raychowdhury, Arijit ; Geuskens, Bibiche ; Tokunaga, Carlos ; Wilkerson, Chris ; Karnik, T. ; De, Vivek

Author_Institution

Intel, Hillsboro, OR, USA

fYear

2010

fDate

7-11 Feb. 2010

Firstpage

282

Lastpage

283

Abstract

A 45 nm 1.3 GHz microprocessor core employs error-detection circuits, tunable replica circuits, and error-recovery circuits, to mitigate dynamic variation guardbands for maximum throughput. An adaptive clock controller adjusts the frequency based on error statistics to optimize efficiency. Silicon measurements show resilient operation as well as throughput gains of 12 to 16% at 1.0 V and 22 to 23% at 0.8 V.

Keywords

error statistics; microprocessor chips; adaptive clock controller; adaptive microprocessor core; dynamic variation tolerance; error statistics; error-detection circuit; error-recovery circuit; frequency 1.3 GHz; resilient microprocessor core; size 45 nm; tunable replica circuit; voltage 0.8 V; voltage 1.0 V; Adaptive control; Clocks; Error analysis; Frequency; Gain measurement; Microprocessors; Programmable control; Silicon; Throughput; Tunable circuits and devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4244-6033-5

Type

conf

DOI

10.1109/ISSCC.2010.5433922

Filename

5433922