Title :
A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration
Author :
Ali, Ahmed M. A. ; Morgan, A. ; Dillon, Chris ; Patterson, G. ; Puckett, Scott ; Hensley, M. ; Stop, Russell ; Bhoraskar, Paritosh ; Bardsley, S. ; Lattimore, D. ; Bray, Joey ; Speir, Carroll ; Sneed, R.
Author_Institution :
Analog Devices, Greensboro, NC, USA
Abstract :
We present a 16b 250MS/S ADC that employs background calibration of the residue amplifier gain errors. It has an integrated input buffer and is fabricated on a 0.18¿m BiCMOS process. Without the input buffer, the SNR is 77.5dB and the SFDR is 90dB. With the input buffer, the SNR is 76dB and the SFDR is 95dB. The clock jitter is 60fs. The ADC consumes 850mW and the input buffer consumes 150mW.
Keywords :
BiCMOS integrated circuits; amplifiers; analogue-digital conversion; buffer circuits; calibration; clocks; jitter; BiCMOS process; IF-sampling pipelined A/D converter; background calibration; clock jitter; integrated input buffer; power 150 mW; power 850 mW; residue amplifier gain errors; size 0.18 mum; time 60 fs; Calibration; Capacitors; Circuits; Digital filters; Energy consumption; Error correction; Linearity; Performance gain; Sampling methods; Voltage control;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5433923
