Title :
A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stacking
Author :
Saito, Masato ; Miura, Naruhisa ; Kuroda, Tadahiro
Author_Institution :
Keio Univ., Yokohama, Japan
Abstract :
128 NAND Flash memory chips and 1 controller chip are stacked using a spiral stair stacking scheme. The controller accesses a random memory chip at 2 Gb/s by inductive-coupling through-chip transmission relayed at every 8th chip. The large coils are placed diagonally over memory core with no area penalty. Energy consumption is reduced to 1.8 pJ/b/chip.
Keywords :
NAND circuits; coupled circuits; flash memories; integrated circuit interconnections; system buses; NAND flash memory stacking; bit rate 2 Gbit/s; controller chip; inductive coupling through chip bus; random memory chip; spiral stair stacking; through chip transmission; Bonding; Coils; Relays; Repeaters; Semiconductor device measurement; Spirals; Stacking; Testing; Transceivers; Transmitters;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5433929
