Design of logarithmic encoder and error corrections

Summary form only given. This paper presents the design of a binary logarithm for a logarithm radix-2 encoder. The circuit implementation uses combinational logic only and is based on Mitchell´s approximation algorithm. The error generated by the Mitchell´s algorithm is analyzed and is used to develop a method to design error correction circuits in order to improve the accuracy of the result. The area and speed characteristics of the proposed circuit design can be shown using an EPF10K20RC240-4 Altera FPGA for implementation. Finally, the error correction circuit that is used to reduce the error in the resulting logarithm approximation can be evaluated and a comparison can be made in the resulting error percentage to show its performance.