Fracture risk assessment for interface flaws in the 3D-interconnect systems of a CMOS chip

The objective of this paper is presenting two energy based failure criteria and applying them in reliability simulations of Complementary Metal Oxide Semiconductor (CMOS) structures. Of particular interest are the Back-End-Of-Line (BEOL) interconnect layers and their interfaces. It is an accepted fact that process-induced flaws due to a mismatch in the Coefficients of Thermal Expansion (CTE) of the involved materials and temperature changes during assembly are unavoidable. The presented approaches use the Finite Element Method (FEM) to calculate the Energy Release Rate (ERR) for interface cracks in these structures. Multi-scale modeling allows dealing with the different length scales of these problems. Some theoretical background information about the approaches is given and a validation of the simulation procedures is performed by means of known reference solutions. An application is shown in which the risk for metal lift failures during wire pull tests is assessed. Different stack designs and metal density configurations are compared. The results show that the calculation of the local ERR with the equivalent domain integral method is a reliable and comparatively inexpensive way to perform delamination risk assessments. In the outlook of this paper some ideas are presented on how the limitations of this method can be dealt with.