Title :
A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O
Author :
Fischette, D.M. ; Loke, A.L.S. ; Oshima, M.M. ; Doyle, B.A. ; Bakalski, R. ; DeSantis, Richard J ; Thiruvengadam, A. ; Wang, C.L. ; Talbot, G.R. ; Fang, E.S.
Author_Institution :
AMD, Sunnyvale, CA, USA
Abstract :
A dual-PLL system for 45 nm SOI-CMOS processors is designed to clock a multi-protocol wireline I/O for high-speed digital communications covering a frequency range from 1 GHz up to 11.1 GHz. The two PLLs, based on a ring and LC-tank VCO, achieve .99 ps and 0.55 ps rms jitter, respectively. Circuit and architectural techniques to minimize the impact of SOI floating-body effect on phase jitter are introduced.
Keywords :
CMOS integrated circuits; UHF circuits; clocks; field effect MMIC; jitter; microprocessor chips; phase locked loops; protocols; silicon-on-insulator; voltage-controlled oscillators; LC-tank VCO; SOI CMOS processors; dual PLL processor clock system; floating body effect; frequency 1 GHz to 11.1 GHz; high-speed digital communications; multiprotocol wireline I/O; phase jitter; size 45 nm; Bandwidth; Circuit noise; Clocks; Filters; Frequency; Jitter; Phase locked loops; Regulators; Voltage; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5433942
