Structural effect of IC plastic package on residual stress in silicon chips

The structural effect of two types of LSI plastic packages, conventional SOJ (small-outline J-lead)-type packages and the newly developed COL (chip on lead)-type packages, on the residual stress in the silicon chip was measured using stress-sensing chips. It was found that the residual stress in the chip encapsulated in the SOJ-type package is determined by the material combinations of the package: resin, lead frame, and the die-attaching paste. The measured stress varied from 50 MPa to 150 MPa at the center of the chip surface. The residual stress in the chip encapsulated in the COL-type package, however, is mainly determined by just the mechanical characteristics of the resin. This is caused by the existence of the polymer film between the chip and the lead frame for electrical isolation. Thermal resistances of these two packages were also measured using stress-sensing chips which have temperature sensors. As outer leads laid under the silicon chip act as cooling fins, the thermal resistance of the COL-type package is about 15°C/W, or 15% to 20% lower than that of the SOJ-type package