Design of 2-D filters for video processing using FPGAs

Image and video processing algorithms implemented in software, require most computation time when the image-size is increased. However, for real time applications the algorithms must be processed at high-speed, for example 2-D filter algorithms. Then, in order to address this inconvenient, the algorithms must be implemented in hardware. In this paper, we present the hardware architectures for 2-D FIR filters and a median filter. The designs are described using generic structural VHDL and synthesized on the FPGA EP2C70F896C6N. The architectures were verified using an image acquisition system based on the D5M camera and the DE2-70 development kit of Terasic.