Title :
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation
Author :
Chun-Cheng Liu ; Soon-Jyh Chang ; Guan-Ying Huang ; Ying-Zu Lin ; Chung-Ming Huang ; Chih-Hao Huang ; Linkai Bu ; Chih-Chung Tsai
Author_Institution :
Nat. Cheng-Kung Univ., Tainan, Taiwan
Abstract :
This paper presents a 10 b SAR ADC with a binary-scaled error compensation technique. The prototype occupies an active area of 155 × 165 ¿m2 in 65 nm CMOS. At 100 MS/S, the ADC achieves an SNDR of 59.0 dB and an SFDR of 75.6 dB, while consuming 1.13 mW from a 1.2 V supply. The FoM is 15.5 fJ/conversion-step.
Keywords :
CMOS integrated circuits; analogue-digital conversion; error compensation; synthetic aperture radar; CMOS integrated circuit; SAR ADC; analog-digital convertsion; binary scaled error compensation; power 1.13 mW; size 65 nm; synthetic aperture radar; voltage 1.2 V; CMOS technology; Capacitance; Capacitors; Circuits; Clocks; Error compensation; Frequency; Logic; Sampling methods; Voltage;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5433970
