A Parallel Feedback Carry Adder Based on Half Adder

This paper proposes a new theory of adder and its basic structure. The new adder is an asynchronous adder whose basic unit is half adder, called Parallel Feedback Carry Adder (PFCA) as its carry mode is parallel feedback. In theory, compared to the adders (e.g. RCA, CLA, CSeA) based on full adder, PFCA is faster in speed and smaller in area. A CMOS gate implementation is proposed to verify the new design theory in this paper. HSPICE simulation results show that PFCA has obvious advantage over RCA, CLA, CSeA in speed and area, showing potential applications especially when adder bits n is larger.