Exploration of a Heterogeneous Concentrated-Sparse On-Chip Interconnect for Energy Efficient Multicore Architecture

We present a novel heterogeneous on-chip interconnect, concentrated-sparse mesh, suitable for high efficiency multicore architectures. The topology is implemented by taking the advantages of both concentrated mesh and sparse mesh networks. The object of the proposed heterogeneous network is to improve performance of the system when running real applications with self-similar, hot-spot and bursty traffic. While regular mesh network has been used widely in on-chip interconnect, concentrated mesh improves average network latency by reducing the number of intermediate network resources. However with high traffic requirements, the limited network bandwidth leads to congestion and performance bottleneck. On the other hand, sparse mesh improves network bandwidth by increasing the number of routers and links, therefore the network can process more hot-spot and bursty traffic than regular and concentrated mesh networks. The weakness of sparse mesh is that, with low traffic injection, the network latency of packets can be higher than other networks. Furthermore the size of the interconnect can become unrealistic for large systems. The proposed heterogeneous interconnect utilizes two networks for processing different traffic. We explore and discuss traffic injection behaviour of several applications. The heterogeneous network is analyzed in details. We investigate a routing algorithm and a mapping algorithm designed for the proposed network. Comparative results are provided by using a full system simulation environment. Results demonstrate that the proposed interconnect improves the average network latency and energy delay product by 15.7% and 44.7%, respectively, compared with regular mesh network.