Title :
POWER7TM local clocking and clocked storage elements
Author :
Warnock, J. ; Sigal, Leonid ; Wendel, Dieter ; Muller, K. Paul ; Friedrich, J. ; Zyuban, V. ; Cannon, E. ; KleinOsowski, A.J.
Author_Institution :
IBM Syst. & Technol. Group, Yorktown Heights, NY, USA
Abstract :
The clocked storage elements and local clocking circuitry for the POWER7TM chip, in 45 nm SOI CMOS technology, include special features for enhanced reliability, testability, and debug capability. Multiple design options, including capacitance-optimized multi-bit layouts, allow for fine-grained power/performance tuning.
Keywords :
CMOS digital integrated circuits; clocks; integrated circuit layout; integrated circuit reliability; integrated circuit testing; silicon-on-insulator; POWER7; SOI CMOS technology; capacitance-optimized multibit layouts; clocked storage elements; debug capability; fine-grained power-performance tuning; local clocking circuitry; reliability enhancement; size 45 nm; Clocks; Counting circuits; Delay effects; Hardware; Latches; Master-slave; Pulse circuits; Silicon on insulator technology; Switches; Testing;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5433995
