DocumentCode
1888525
Title
Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor
Author
Dighe, S. ; Vangal, Sriram ; Aseron, Paolo ; Kumar, Sudhakar ; Jacob, Tony ; Bowman, Keith ; Howard, John ; Tschanz, James ; Erraguntla, V. ; Borkar, N. ; De, Vivek ; Borkar, Shekhar
Author_Institution
Intel, Hillsboro, OR, USA
fYear
2010
fDate
7-11 Feb. 2010
Firstpage
174
Lastpage
175
Abstract
Measured within-die core-to-core F?????? variation data for an 80-core processor in 65 nm is presented. Variation-aware DVFS with optimal core mapping is shown to improve energy efficiency 6 to 35% across a range of compute/communication activity workloads. A dynamic-thread-hopping scheme boosts performance by 5 to 10% and energy efficiency by 20 to 60%.
Keywords
multiprocessing systems; power aware computing; 80-core processor; F?????? variation data; communication activity workloads; dynamic thread hopping scheme; dynamic voltage frequency scaling core mapping; energy efficiency; variation aware DVFS; Circuits; Clocks; Communication switching; Energy efficiency; Energy measurement; Network-on-a-chip; Performance gain; Rails; Voltage; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
978-1-4244-6033-5
Type
conf
DOI
10.1109/ISSCC.2010.5433997
Filename
5433997
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